Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits

A single path delay fault of a circuit is reduced to a fault in the literal in the equivalent normal form (ENF) that corresponds to the path that acts during the path delay. Based on the analysis of the ENF circuit, we have found properties of pairs of robust and nonrobust test vectors. We show possibilities to reduce the length of the test for path delay faults.

Presented by the member of Editorial Board: P. Yu. Chebotarev