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JOURNALS // Avtomatika i Telemekhanika // Archive

Avtomat. i Telemekh., 2021 Issue 11, Pages 148–168 (Mi at15834)

This article is cited in 2 papers

Optimization, System Analysis, and Operations Research

Constructing a sequence detecting robustly testable path delay faults in sequential circuits

A. Yu. Matrosova, S. V. Cherhyshov, O. Kh. Kim, E. A. Nikolaeva

Tomsk State University, Tomsk, 634050 Russia

Abstract: We propose a method for constructing a sequence of Boolean vectors of input variables that delivers test pairs $(v_1,v_2)$ of neighboring vectors in the space of input and internal variables for robustly testable path delay faults (robust Path Delay Faults (PDFs)) in sequential logic circuits. The purpose of this work is to clarify the possibility of constructing a test sequence for a given subset of paths without using scanning technologies, i.e., without additional hardware costs within the constraint of the sequence length for a single path. The experiments carried out show that test sequences can be constructed not for all paths (sometimes for none) for which test pairs exist in the combination component of the sequential circuit.

Keywords: sequential logic circuit, homing sequence, Reduced Ordered Binary Decision Diagram (ROBDD), robustly testable path delay fault (PDF), rising (falling) transition.

Presented by the member of Editorial Board: M. F. Karavai

Received: 22.05.2020
Revised: 01.02.2021
Accepted: 16.03.2021

DOI: 10.31857/S0005231021110106


 English version:
Automation and Remote Control, 2021, 82:11, 1949–1965

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© Steklov Math. Inst. of RAS, 2024