Linear decision diagram based mapping for rapid prototyping

The paper focuses on the methodology of generating a high-level circuit description, Linear Decision Diagrams (LDDs), from a popular Electronic Design Interchange Format (EDIF), and mapping this LDD-based description, onto a circuit netlist associated with rapid prototyping, Xilinx Netlist Format (XNF). A synthesis step that produces an XNF enables further technology mapping using Xilinx tools. The results of an experimental study on design of LDD models and transformation to/from EDIF and to XNF are reported here.

Presented by the member of Editorial Board: P. P. Parkhomenko