Pseudorandom test pattern generators for built-in self-testing: a power reduction method

A method of reducing the power consumption of a pseudorandom test pattern generator for scan-based built-in self-tests of digital devices is designed on the basis of formation of several test symbols in one operation cycle of the circuit.A new structure for low-power test pattern generators is described.

Presented by the member of Editorial Board: P. P. Parkhomenko