Functional tests for RISC-microprocessors

The well-known models and concepts of functional testing of microprocessors are described. The properties of the RISC-architecture that aid in applying effective approaches to hardware testing are stated. Functional decomposition is used to develop a sequence of actions implemented in designing tests. Special attention is paid to testing of control units. The RISC-architecture has shown to be helpful in designing effective algorithms for testing at the architectural level. The designed procedures detect most of the defects in control circuits indirectly through data processing and storing devices without the use of control units.

Presented by the member of Editorial Board: V. V. Kul'ba