This article is cited in 1 paper

Technical Diagnostics

A test algorithm for multiple-valued logic combinational circuits

V. Levashenko^a, K. Moraga^b, G. Kholovinski^c, S. N. Yanushkevich^c, V. P. Shmerko<sup>d

a</sup> Belarusian State Economic University
^b Universität Dortmund, Institut für Mathematik
^c University of Szczecin
^d Belarussian State University of Computer Science and Radioelectronic Engineering

UDC: 681.3.16.519.714.24

Presented by the member of Editorial Board: P. P. Parkhomenko

Received: 20.07.1998

 English version: Automation and Remote Control, 2000, 61:5, 844–857

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