One procedure for designing $s$-fault-tolerant discrete devices

The paper proposes a way to design $s$-fault tolerant discrete circuits with a memory whereby the states of system elements are encoded with a systematic code and the faults are detected and corrected through formation of syndromes insensitive to faults of any their $s$ elements. An example of discrete circuits design in which $s$ is equal to one is given. The technique proposed is shown to reduce the amount of additional facilities, compared with conventional techniques, in the case of linear switching circuits.