Development of tests for VLSI circuit testability at the upper design levels

The state-of-the-art in testing of the very large scale integrated (VLSI) circuits was analyzed. Consideration was given to the directed construction of tests at the system level of presentation of the object or the register transfer level in the VHDL language. The class of functional faults considered at the directed construction of a test corresponds to the bit-stuck faults of the VLSI circuit realizations with the elements of the corresponding design libraries. Proposed was a method of directed test design enabling one at the earlier stages of design to analyze testability vs. the technological design libraries used.

Presented by the member of Editorial Board: P. P. Parkhomenko