RUS  ENG
Full version
JOURNALS // Diskretnaya Matematika // Archive

Diskr. Mat., 2017 Volume 29, Issue 4, Pages 87–105 (Mi dm1451)

This article is cited in 13 papers

A method of synthesis of irredundant circuits admitting single fault detection tests of constant length

D. S. Romanova, E. Yu. Romanovab

a Lomonosov Moscow State University
b Russian State Social University, Moscow

Abstract: A constructive proof is given that in each of the bases $B'=\{ x\mathbin{\&} y, x\oplus y, x\sim y\}$, $B_1=\{ x\mathbin{\&} y, x\oplus y, 1\}$ any $n$-place Boolean function may be implemented: a) by an irredundant combinational circuit with $n$ inputs and one output admitting (under single stuck-at faults at inputs and outputs of gates) a single fault detection test of length at most 16, b) by an irredundant combinational circuit with $n$ inputs and one output admitting (under single stuck-at faults at inputs and outputs of gates and at primary inputs) a single fault detection test of length at most $2n-2\log_2 n+O(1)$; besides, there exists an $n$-place function that cannot be implemented by an irredundant circuit admitting a detecting test whose length is smaller than $2n-2\log_2 n-\Omega(1)$, c) by an irredundant combinational circuit with $n$ inputs and three outputs admitting (under single stuck-at faults at inputs and outputs of gates and at primary inputs) a single fault detection test of length at most 17.

Keywords: circuit of gates, fault detection test, stuck-at fault, Shannon function, easily testable circuit.

UDC: 519.718

Received: 23.08.2017
Revised: 06.11.2017

DOI: 10.4213/dm1451


 English version:
Discrete Mathematics and Applications, 2019, 29:1, 35–48

Bibliographic databases:


© Steklov Math. Inst. of RAS, 2024