Abstract:
A method for obtaining lower bounds for the complexity of gate circuits by construction of compressed semimetrics in algebras of realizable schemes of objects is recommended. The method allows one to obtain superpolynomial lower bounds for monotone circuits and certain new bounds for other (nonmonotone) circuits. A lower bound $\exp((\log_2 n)^2)$ for a certain class of circuits over the basis $\{\&,\vee,^-\}$ and a lower bound of order $\exp(n^{1/4})$ for circuits over certain three-valued extensions of the basis $\{\&,\vee,^-\}$ are given.