Synchronous and self-timed pipeline's reliability estimation

Self-timed (ST) circuitry is an alternative to synchronous circuits. Self-timed circuits have a number of advantages over their synchronous counterparts due to their redundant complexity. The article investigates the immunity of self-timed and synchronous circuits to single short-term soft error taking into account the hardware redundancy of ST circuits. Self-timed circuits, due to their indication subcircuit, are able to detect a soft error which occurs as a logical cell's output state inversion and suspend the operation of the circuit until the soft error disappears. Thus, ST circuits mask a single soft error and prevent distortion of the data processing result. The use of a modified hysteretic trigger, which prevents sticking in the antispacer, to implement a pipeline stage register bit masks almost all soft errors in the pipeline stage's combinational part. The DICE-like implementation of this trigger makes it possible to reduce the sensitivity of the ST register to the internal soft errors by a factor of 4. Quantitative estimates of failure tolerance show a clear (by 2.5–9.4 times) advantage of the ST pipeline in comparison with the synchronous counterpart.