Multioption redundancy taking into account logical and topological features of transistor circuit

Passive fault tolerance of digital cells and devices is considered using multioption reliability taking into account features of the transistor redundancy topological simulation. A model is built that includes channel majority redundancy with the majority voters redundancy, allowing for the channel “collapse” during diagnostics, deep redundancy with redundancy at the level of individual channel's layers with special majority voters that ensure the configuration of layers into channels. The known methods are combined in a relationship that optimizes a given objective function with the required constraints. In addition, redundancy is used at the individual transistor level with varying degrees of failure protection. The topological features of such reservation are investigated by constructing various variants of circuits based on disjunctive normal, conjunctive normal, and intermediate forms. The power of the set of such variants is established. A method for searching for the topologically best variant with a large device dimension is proposed. By means of topological modeling, the preferred backup option is established based on the indicator of the consumed power and the switching delay product. Parameters examples of created topologies are given.