A method of synthesizing irredundant circuits, admitting small single fault diagnostic test sets at stuck-at faults at outputs of gates

Background. Testing of combinational circuits is an important theoretical problem with applications in testing and verification of VLSI. The aim of this work is to demonstrate that for an arbitrary Boolean function it is possible to construct a circuit realizing this function and allowing small single fault diagnosing test set (at stuck-at faults at outputs of gates). Materials and methods. Circuit design methods based on Zhegalkin polinomials (canonical Reed-Muller polinomial forms) were used. Results. It is established that for an arbitrary Boolean function $f$ depending on $n$ variables there exists an irredundant combinational circuit (in the basis $\{x \& y, x\oplus y, 1\}$) realizing $f$ and admitting a single fault diagnosing test set (at stuck-at faults at outputs of gates) with constant cardinality.