Spatial inhomogeneity of impact-ionization switching of power silicon thyristors

Research has been carried out on the process of switching a power silicon thyristor with a voltage pulse. It has been established that when the voltage rise rate dU/dt increases from 1 to 10 kV/ns, the switching voltage increases from 3 to 7 kV, and the duration of the switching process is reduced to 200 ps. A thyristor with a pre-applied bias voltage has a shorter duration and a higher switching voltage compared to a thyristor without it. At $dU/dt$ > 4 kV/ns, the switching voltage of the thyristor without bias becomes more than that of the thyristor with bias, which is associated with saturation of the carrier velocities in the neutral part of the $n$-base. Simulation has shown that the calculated and experimental voltage oscillograms have quantitative agreement in the case when the value of the active area of the structure through which the switching current passes increases with increasing $dU/dt$, approaching the total area of the device at $dU/dt$ > 10 kV/ns and tends to zero at $dU/dt$ < 1 kV/ns. It is shown that spatial inhomogeneity of the current distribution arises at the stage of formation of the impact-ionization front in a region depleted of majority charge carriers. The size of the active area is proportional to the maximum intensity of ionization processes in this time interval.