A low-power digitally controlled oscillator based on 65-nm CMOS technology

This paper contains the research results related to the Master thesis about the design of Dual band Differential Digital Ring oscillator (DRO) in two stages, describing the lower power consumption, smaller area, lower phase noise, linear frequency range and better frequency stability with variation of applied voltage, in addition to the investigation of the temperature variation effect. We have proposed a circuit using the 65-nm CMOS process with Radio Frequency (RF) transistors and the output frequency digitally controlled (by 4-bit (coarse), 3-bit (fine) tuning) as control code, for the low-band frequency range [1.487–3.021 GHz] and power consumption of 0.359 mW @ 2.42 GHz, and for the high-band frequency range [3.5–6.98 GHz] and the power consumption of 1.86 mW @ 6.023 GHz, the band gap between two bands equal to 500 MHz, the phase noise about –84.4 dBc/Hz @ 1MHz, and the jitter value of 4.335 ps, with FOM equal to –156.5 dBc/Hz.