Efficiency analysis of high-level synthesis tools for hardware implementation of sorting algorithms

The article is devoted to the research of efficiency of Xilinx's high-level synthesis tools, the Vivado HLS package version 2019.2, for synthesis of a hardware implementation of sorting algorithms. The relevance of creating hardware implementation of sorting algorithms is determined by modern approaches to building high-performance heterogeneous computing systems and modern criteria for the efficiency of such systems – the ratio of performance to power consumption and the ratio of real performance to peak performance. The authors carried out a comparative analysis of the implementation of the selected sorting algorithms on a universal processor and on the basis of the VLSI Xilinx submarine research. The article discusses approaches to optimize the description of algorithms and control the Vivado HLS package to achieve optimal performance of the resulting hardware solutions. The article shows that the main performance gain is provided by parallelizing of the source arrays processing, which is achieved both by the settings of the design tool, the Vivado HLS package, the selected description style, as well as the features of the sorting algorithm selected for hardware implementation.