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JOURNALS // Prikladnaya Diskretnaya Matematika // Archive

Prikl. Diskr. Mat., 2009 supplement № 1, Pages 65–66 (Mi pdm70)

This article is cited in 1 paper

Mathematical Foundations of Reliability of Computing and Control Systems

Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method

V. V. Andreeva, A. Yu. Matrosova, A. V. Mel'nikov, A. V. Morozova


Abstract: Combinational circuit obtained from irredundant system with factorized synthesis method is considered. The conditions of a path delay fault manifestation as robust, non-robust and functional one are detected. Deriving test pairs for path delay fault is reduced to finding test patterns for $a,b$-faults of prime implicants. It allows combining test for single faults of irredundant system (that is test for multiple stuck-at faults at the gate poles of the circuit) with test for path delay faults.

UDC: 681.324.7



© Steklov Math. Inst. of RAS, 2025