Abstract:
When creating computer boards with FPGA or application-specific
chips, it is often needed to connect several chips. Existing available buses do not
have all the properties required by the authors' task at hand: packet transmission,
using a small number of GPIO pins, sufficient bandwidth.
We describe a packet communication protocol that uses GPIO pins and has
bandwidth up to 10 MB/s at a frequency of 20 MHz.
Key words and phrases:half-duplex communication, credit-based flow control, data serialization/deserialization, finite state machine, shift register, hardware description language.
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