G. P. Aksenova, “The matrix test response analysis technique for FPGA”, Probl. Upr., 2014, Issue 5,Pages <nobr>65

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The matrix test response analysis technique for FPGA

G. P. Aksenova

Institute of Control Sciences, Russian Academy of Sciences, Moscow

Abstract: Test response analysis techniques using a signature analyzer are considered. A new analysis technique that provides a fault location and a low hardware overhead is proposed.

Keywords: application-specific integrated circuit (ASIC), field-programmable gate array, on-line testing, circuit under test, test response analysis, signature analyzer, fault location.

UDC: 681.325