Dataflow architecture model and its usage with a word recognizer program as an example

The imitational model of the dataflow recurrent architecture that is being implemented as application-specific integrated circuit at field-programmable gate array platform designed by Altera, is presented. This model lets the user to perform the debugging of the architecture's functional blocks before the hardware implementation and serves as an instrument of software development and debugging. The architecture key aspects, specialized programming language, and their projection at the model are also presented.