Self-timing analysis of electronic circuits on the lower level of hierarchy

Self-timed circuits (independent on element's delay) have the unique properties of a lack of competitions and safe on Out-Stack-At-Fault (OSAF). They require analysis on self-timing. In the traditional approach — analyzing of elements switching, computational complexity is so great that it does not allow analyzing the most practical circuits. The functional hierarchical method, previously proposed by the author, analyzes logic equations only at the lower level, and at the upper levels, it examines only the relationships between blocks. The suggested method makes it possible to analyze circuits of any size effectively. This article describes in detail this method at the lower level of the hierarchy.