A method of packet processing in integrated network processors

The article introduces a method of packet processing in integrated network processors with conventional core architectures. Packets are processed in an internal “virtual” pipeline, with available hardware resources being its stages. The classifier determines the route of a specific packet, and the latter follows the route under control of an assigned resource — the queue manager. In addition to general pipeline control, the manager resolves access contentions to hardware resources and provides packets with quality of service. Interaction between the queue manager and hardware resources involved into the internal pipeline is carried out uniformly through composite queues of buffer, frame, and packet descriptors. Bodies of the composite queues are arranged in a system memory while their heads or tails (depends on the queue direction) are implemented as hardware FIFO (First-In/First-Out) aligning processing rates of the queue manager and managed hardware resources of the internal pipeline.