A way to enhance throughput of packet switches built on the basis of integrated network processors

Permanent perfection and complication of protocols related to quality of service and network security forces packet switches' creators to shift their preferences from the hardware packet forwarding to soft switching methods and, implementing these methods, to programmable devices with additional network functionality. From this standpoint, network processors represent practically ready to use inexpensive programmable switches realizing the concept of switching on shared memory. Alongside with many merits, this concept has an intrinsic throughput limitation resulting from the memory sharing itself. A subsystem for buffering network frames and packets, which could be integrated into a network processor, removes this limitation and enables the latter to implement easily a programmable switch with an essentially higher potential throughput and all merits of switching on shared memory preserved.