Abstract:
Functional specificity of the self-timed circuits makes special
requirements to their characterization procedure. This procedure should take into
account a signal conditioning discipline for information and phase signals on base of
user defined attributes of the characterized cell's inputs and outputs. The paper
describes a technique of adjusting characterization process for sequential self-timed
cells. It is based on using vectors that set static values and transition direction for all
inputs and outputs. Algorithmization and implementation of the suggested approach
in new SAHIB characterization system version have increased its efficiency and
provided the valid characterization of all sequential cell types in the self-timed cell
library for 65-nanometer standard CMOS (complementary
metal-oxide-semiconductor)
process. Automatic introduction of the Verilog
constructions analyzing change order of all cell inputs and notifying their invalid
sequence into the sequential cell models during characterization procedure
accelerates and mitigates self-timed circuit design.