Self-timed pipeline's soft error tolerance analysis

Practical self-timed (ST) circuits are implemented as a pipeline, similar to synchronous circuits. Self-timed circuits have a number of advantages in comparison with synchronous counterparts but are redundant in hardware. The article analyzes the tolerance of the ST pipeline to single soft errors, taking into account its hardware redundancy and assuming that each soft error affects only one circuit's logical cell. Due to their two-phase work discipline and the mandatory indication of the successful completion of the switching in each phase, the ST circuits can detect a soft error and suspend the operation of the circuit until it disappears. A failure-tolerant hysteretic latch as a part of the pipeline stage register bit ensures that the register is immune to any soft error in the pipeline stage's combinational part. The DICE-like implementation of this latch increases the ST register tolerance to internal soft errors by a factor of 2.7. In general, the ST pipeline is 2.5–6.8 times more immune to single soft errors than its synchronous counterpart.