Self-timed sequential circuits: Development experience and design guideline

Self-timed (ST) circuits actively go over from theoretical research field into the area of practical projects finding their implementations in the wide assortment of computing devices. This is due to such features of the ST-circuits as independence of working capacity on delay of device components, natural reliability, working capacity in significantly wider range of varied environmental factors and power supply voltage. This paper describes the guidelines on designing sequential ST-circuits implemented on CMOS (complementary-metal-oxide-semiconductor) technology base. The comparative analysis of the characteristics of sequential synchronic and ST-circuits obtained by means of simulation and practical experiments of the test chips is represented. Test results prove that usage of ST-circuitry provides an improvement of the characteristics of sequential circuits, especially for their fault-tolerant implementations.