Combined encoding in elements of field-programmable gate arrays

The authors consider the variables' combined coding of a Lookup Table (LUT) logical element and a routing multiplexer that is an interconnect switch of the Field-Programmable Gate Array (FPGA). The proposed method of combining positional and unitary coding ensures the reduction of the logical function calculation delay under given hardware limitations or the reduction of the communication switch hardware costs under restrictions on the delay. The paper describes a model of such encoding and a method for synthesizing the corresponding element. It provides complexity estimates in terms of transistors and results of circuit and layout simulation. Simulation proves the proposed element's performance. The analysis shows the effectiveness of the adopted approach in terms of complexity, layout area, time delay, and power consumption. The developed element with combined encoding can significantly reduce the time delay when calculating functions of a large variable number and the interconnect configuration memory volume.