Cut-based technology mapper with optimizations

This paper addresses the problem of constructing an optimization-oriented technology mapper for logic synthesis. We present an implementation of a cut-based technology mapper developed within the Utopia EDA project, a prototype logic synthesis tool distributed under Apache 2.0 license. The proposed mapper is based on Boolean matching and supports multiple optimization objectives, including area (the total area of instantiated standard cells), power (the estimated total power consumption of the synthesized design), and timing (the estimated critical-path delay). It should be noted that targeting one objective implies accounting for constraints on the other two objectives. We provide a comparison with the technology mapper used in the OpenLane flow. Experimental results obtained on a benchmark set of thirty-one RTL designs (Verilog/SystemVerilog) demonstrate that, in the majority of cases, the proposed optimizations outperform the Yosys-based technology mapping used in OpenLane with respect to area and power. For timing optimization, the results are different, indicating directions for future work.