Parallel implementation of the algorithm for correction of antenna rule violations in openlane design flow

The open IC design flow OpenLane make available the RTL-to-GDS design flow to be implemented, but still some tasks remain unsolved. An example of such task is the correction of antenna rules violations. The detection tools for this procedure are the part of the OpenLane flow but it does not contain any tools for avoiding them. In this article the software is presented that has been developed and allows to avoid violations of antenna rules based on input data in the form of LEF file with information about the standard cell library and DEF file with information about the placement and routing of the design. A parallel implementation is also described; we show the results of more than 60% gain in time with using parallel version in comparison with sequential version. The article describes both the developed algorithm and the software built on its basis, the capability of embedding into an open OpenLane flow, and an example of embedding script code. The use of the developed software makes it possible to correct a significant part of antenna rules violations, thereby increasing the yield.