System for static analysis of SystemVerilog HDL

The growing complexity of modern digital systems and the increasing volumes of code written in hardware description languages demand effective tools for early error detection in the development of digital ASICs. To facilitate timely error detection, rule sets are created to regulate hardware descriptions. These rule sets contain a collection of rules that describe inaccuracies, errors, and the consequences of their violation. This paper discusses a list of rules developed based on the experience of engineers using the SystemVerilog language and presents the SVAN static analysis system, designed for SystemVerilog and tailored to the specifics of hardware descriptions. The proposed system provides full support for the SystemVerilog IEEE 1800-2017 standard and offers capabilities for analyzing descriptions for structural and semantic errors.