Netlist-based ASIC area and delay prediction using machine learning

Hardware development is a time-consuming process that includes logic synthesis, placement and routing as its main steps. Despite that these steps are automated in modern CADs, their execution can take hours or even days. The application of machine learning methods can help predict synthesis results and thereby speed up the development process. This article describes the experience of creating and evaluating eight machine learning models for predicting area and delay of the synthesized ASIC using its netlist at the logic synthesis step. The results obtained show the benefits of this approach and indicate directions for further research.