Application of neural networks for routing congestion prediction in VLSI design using initial layout parameters

This paper considers the problem of congestion map prediction at the pre-routing stage of VLSI layout design of digital blocks by applying neural network models. Early prediction of congestion will allow the VLSI design engineer to modify floorplan, macro placement and input-output port placement to prevent interconnect routing issues at later stages, thereby reducing the number of EDA tool runs and the overall circuit design runtime. In this work we propose the use of the initial layout parameters, which were not considered in previous works and allow for a more accurate congestion prediction.