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JOURNALS // Vestnik Yuzhno-Ural'skogo Universiteta. Seriya Matematicheskoe Modelirovanie i Programmirovanie // Archive

Vestnik YuUrGU. Ser. Mat. Model. Progr., 2010 Issue 6, Pages 41–53 (Mi vyuru227)

This article is cited in 1 paper

Russian 3D-torus interconnect with globally addressable memory support

A. A. Korzha, D. V. Makagona, A. A. Borodin, I. A. Zhabin, E. R. Kushtanov, E. L. Syromyatnikov, E. V. Cheryomushkina

a Scientific and Research Centre of Electronic Computer Technology, Moscow

Abstract: This paper gives the overview and early results of prototyping of the 3D-torus interconnect developed in NICEVT, Moscow. This interconnect was designed to be equally effective in small-size computing clusters and petascale systems. The key features of the interconnect are high fault-tolerance, high message rate per core supported by host adapter and hardware support for globally addressable memory provided via SHMEM parallel programming library.

Keywords: interconnection network, supercomputer, 3D-torus, globally addressable memory.

UDC: 004.72

Received: 07.04.2010



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