D. V. Dubrov, A. S. Roshal, B. Ya. Steinberg, R. B. Steinberg, “Automatic mapping programs onto a processor with an FPGA accelerator”, Vestn. YuUrGU. Ser. Vych. Matem. Inform., 2014, Volume 3, Issue 2,Pages <nobr>117

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Brief Reports

Automatic mapping programs onto a processor with an FPGA accelerator

D. V. Dubrov, A. S. Roshal, B. Ya. Steinberg, R. B. Steinberg

Southern Federal University (Rostov-on-Don, Russian Federation)

Abstract: A problem of automatic high level program mapping onto a CPU with an FPGA accelerator is considered in this work. For such a mapping an HDL code generator from a parallelizing system's internal representation is being developed and used.

Keywords: social network analysis, information retrieval, data mining, expert finding, popularity analysispeline computing, high-level synthesis, parallelizing compiler, FPGA, VHDL.

UDC: 681.3

Received: 07.03.2014