Static analysis of power intent in integrated circuits

With the increasing number of electrical components and integrated circuits’ physical size reduction, organizing the energy-efficient operation of digital hardware has become significantly more complex. Traditional hardware description languages Verilog/SystemVerilog and VHDL lack the means for effectively defining and optimizing the description of the power intent. To address this issue, the IEEE 1801 standard introduced the Unified Power Format (UPF), which allows for the formalization of the power management structure and rules in digital systems. However, most modern EDA tools that support the interpretation of UPF descriptions are commercial and often exhibit deviations from the standard, whereas non-commercial tools significantly lag behind their commercial counterparts in terms of language command support and rarely include power intent analysis capabilities. This paper presents a tool for interpreting UPF descriptions and performing static analysis of the power intent model that fully supports the IEEE 1801-2018 standard.