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References
|
|
|
1. |
Pomeranz I., Reddy S. M., “On the generation of small dictionaries for fault location”, Proc. of the 1992 IEEE/ACM Intern. Conf. on Computer-Aided design
(ICCAD '92). Los Alamitos, CA, USA, 1992, 272–279 |
2. |
Arslan B., Orailoglu A., “Fault dictionary size reduction through test response superposition”, Proc. of the 2002 IEEE Intern. Conf. on Computer Design: VLSI in
Computers (ICCD'02). Washington, DC, USA, 2002, 480–485 |
3. |
Boppana V., Hartanto I., Fuchs W. K., “Full fault dictionary storage based on labeled tree encoding”, Proc. of 14th VLSI Test Symposium. Washington, DC, USA, 1996, 174–179 |
4. |
Abramovici M., Breuer M. A., Friedman A. D., Digital Systems Testing and Testable Design, Computer Science Press, Inc., N.Y., 1996 |
5. |
Yarmolik V. N., Kontrol i diagnostika tsifrovykh uzlov EVM, Nauka i tekhnika, Minsk, 1988 |
6. |
Ryan P. G., Fuchs W. K., Pomeranz I., “Fault dictionary compression and equivalence class computation for
sequential circuits”, Proc. of IEEE Intern. Conf. on Computer-Aided Design (ICCAD'93). Los
Alamitos, CA, USA, 1993, 508–511 |
7. |
Boppana V., Fuchs W. K., “Fault dictionary compaction by output sequence removal”, Proc. of the 1994 IEEE/ACM Intern. Conf. on Computer-aided design
(ICCAD '94). Los Alamitos, CA, USA, 1994, 576–579 |
8. |
Chess B., Larrabee T., “Creating small fault dictionaries”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 18:3 (1999), 346–356 |
9. |
Malyshenko Yu. V., Razdobre A. Kh., “Metod sokrascheniya ob'ema diagnosticheskoi informatsii, ispolzuemoi dlya
poiska neispravnostei”, Avtomatika i telemekhanika, 1977, no. 4, 160–164 |
10. |
Speranskii D. V., Shatokhina N. K., “Metody optimizatsii diagnosticheskoi informatsii”, Teoreticheskie problemy kibernetiki, Izd-vo Sarat. un-ta, Saratov, 1986, 129–132 |
11. |
Chipulis V. P., “Metody minimizatsii razreshayuschei sposobnosti i diagnosticheskoi informatsii”, Avtomatika i telemekhanika, 1975, no. 3, 133–141 |
12. |
Chipulis V. P., “Issledovanie diagnosticheskoi informatsii pri kontrole i poiske
neispravnostei diskretnykh ustroistv”, Avtomatika i telemekhanika, 1975, no. 8, 150–157 |
13. |
Chipulis V. P., “Metody predvaritelnoi obrabotki i formy zadaniya diagnosticheskoi
informatsii dlya poiska neispravnostei diskretnykh ustroistv”, Avtomatika i telemekhanika, 1977, no. 4, 165–175 |
14. |
Speranskii D. V., Shatokhina N. K., “Priblizhennye metody resheniya zadach optimizatsii glubiny diagnostirovaniya
diskretnykh ustroistv”, Mnogoprotsessornye vychislitelnye struktury, 7(XIV), Izd-vo Taganr. radiotekhn. in-ta, Taganrog, 1985, 70–72 |
15. |
Voznesenskii S. S., Razdobreev A. Kh., “Trudoemkost poiska neispravnostei kak kriterii kachestva pri sokraschenii
ob'ema diagnosticheskoi informatsii”, Elektronnoe modelirovanie, 1980, no. 4, 83–86 |
16. |
Barashko A. S., Skobtsov Yu. A., Speranskii D. V., Modelirovanie i testirovanie diskretnykh ustroistv, Nauk. dumka, Kiev, 1992 |
17. |
Speranskii D. V., “Ob odnom podkhode k resheniyu zadach sokrascheniya ob'ema diagnosticheskoi
informatsii”, Avtomatika i telemekhanika, 1984, no. 3, 151–160 |
18. |
Sharshunov S. G., “Osobennosti diagnoza tekhnicheskogo sostoyaniya mnogovykhodnykh ob'ektov
s ispolzovaniem tablits neispravnostei”, Avtomatika i telemekhanika, 1973, no. 12, 161–168 |
19. |
Quinlan J. R., C4.5: programs for machine learning, Morgan Kaufmann Publishers Inc., San Francisco. CA, USA, 1993 |
20. |
Brglez F., Bryan D., Kozminski K., “Combinational profiles of sequential benchmark circuits”, Proc. of Intern. Symposium on Circuits and Systems. Portland, OR, USA, 1989, 1929–1934 |
21. |
Niermann T., Patel J., “HITEC: a test generation package for sequential circuits”, Proc. of European Design Automation Conf. Los Alamitos, CA, USA, 1991, 214–218 |