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Publications in Math-Net.Ru
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Comparison of high-level synthesis and hardware construction tools
Proceedings of ISP RAS, 34:5 (2022), 7–22
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Comparison of open flows for digital hardware development: qflow, openlane, coriolis, and symbiflow
Proceedings of ISP RAS, 33:6 (2021), 111–130
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Architecture of a machine code deductive verification system
Proceedings of ISP RAS, 32:3 (2020), 7–19
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Extracting assertions for conflicts in HDL descriptions
Proceedings of ISP RAS, 31:3 (2019), 135–144
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Test generation for digital hardware based on high-level models
Proceedings of ISP RAS, 29:4 (2017), 247–256
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MicroTESK-based test program generator for the ARMv8 architecture
Proceedings of ISP RAS, 28:6 (2016), 87–102
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Specification-based test program generation for MIPS64 memory management units
Proceedings of ISP RAS, 28:4 (2016), 99–114
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Checking parameterized Promela models of cache coherence protocols
Proceedings of ISP RAS, 28:4 (2016), 57–76
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A method of extended finite state machines construction from HDL descriptions based on static analysis of source code
St. Petersburg Polytechnical University Journal. Computer Science. Telecommunication and Control Sys, 2015, no. 1(212), 60–73
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An extended finite state machine-based approach to code coverage-directed test generation for hardware designs
Proceedings of ISP RAS, 27:3 (2015), 161–182
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A model-based approach to design test oracles for memory subsystems of multicore microprocessors
Proceedings of ISP RAS, 27:3 (2015), 149–160
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An approach to test program generation based on formal specifications of caching and address translation mechanisms
Proceedings of ISP RAS, 27:3 (2015), 125–138
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Verifying correctness of hdl-model behavior on the basis of dynamical trace matching
St. Petersburg Polytechnical University Journal. Computer Science. Telecommunication and Control Sys, 2014, no. 2(193), 130–142
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Foreword
Proceedings of ISP RAS, 27:3 (2015), 7–8
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