Speciality: 05.13.11 (Mathematical and programme software for computers, computer systems, and networks)
Birth date: 7.07.1956
Phone: +48 516 038 349, +375 29 313 3262
Keywords: design technologies, synthesis, optimization, finite state machines, combinational circuits, standard functional blocks, structural models of FSMs, low-power design technologies, architectures of CPLD, FPGA, and SoC, Verilog and VHDL languages, microcontrollers, embedded systems, high-speed digital systems.
UDC: 004.312.4

Subject:

design technologies for integrated circuits and systems, synthesis finite state machines (FSMs), combinational circuits, standard functional blocks, structural models of FSMs, low-power design technologies, architectures of CPLD, FPGA, and SoC, Verilog and VHDL languages, microcontrollers, embedded systems, high-speed digital systems.

Main publications:

1. Solovev V.V., “Minimizatsiya konechnykh avtomatov Mili putem ispolzovaniya znachenii vykhodnykh peremennykh dlya kodirovaniya vnutrennikh sostoyanii”, Izvestiya Rossiiskoi akademii nauk. Teoriya i sistemy upravleniya, 2017, № 1, 89-97
2. Solovev V.V., “Proektirovanie na programmiruemykh logicheskikh integralnykh skhemakh bystrykh komparatorov bolshoi razryadnosti”, Problemy razrabotki perspektivnykh mikro- i nanoelektronnykh sistem, т. I, IPPM RAN, M., 2016, 24-31
3. Salauyou V., “Synthesis of high-speed finite state machines in FPGAs by state splitting”, Proc. of the 15th IFIP TC8 International Conf. Computer Information Systems and Industrial Management, CISIM 2016, (Vilnius, Lithuania, September 14-16, 2016), Springer, 2016, 741-751
4. Solovev V.V., Arkhitektury PLIS firmy Xilinx: CPLD i FPGA 7-i serii, Goryachaya liniya – Telekom, M., 2016
5. Solovev V.V., Proektirovanie tsifrovykh sistem na osnove programmiruemykh logicheskikh integralnykh skhem, Goryachaya liniya – Telekom, M., 2001

Publications in Math-Net.Ru

Personal pages:

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Organisations:

• Belarusian State Academy of Telecommunications