Speciality:
05.13.18; 05.13.17 (Mathematical modeling, numerical methods, and the program systems; Theoretical foundation for informatics)
Keywords: VLSI, SoC, simulation, verification, tests, logical coding, faults
Subject:
Modeling of VLSI at different design levels.
Verification of projects and development of tests of VLSI control at RTL-, functional-logical and switching levels.
Main publications:
L.A. Zolotorevich, “Project verification and construction of superchip tests at the RTL level”, Automation and Remote Control, 74:1 (2013), 113-122
Zolotorevich L.A., Il'inkova A. V., “Development of tests for VLSI circuit testability at the upper design levels Automation and Remote Control.”, Automation and Remote Control, 71:9 (2010), 1888-1898
Zolotorevich, L.A., Yukhnevich D.I., “Switch-level VLSI quasistatic simulation methods: Comparative accuracy of models”, Automation and Remote Control, 9:9 (1998)
