Egorov Vladimir Borisovich

Publications in Math-Net.Ru

1. Evolution of the “software-defined” concept
   
   Sistemy i Sredstva Inform., 34:2 (2024),  83–94
2. Some networking aspects of software-defined cloud platforms
   
   Sistemy i Sredstva Inform., 34:1 (2024),  102–110
3. Some issues of disaggregation and composability of the data center infrastructure
   
   Sistemy i Sredstva Inform., 33:2 (2023),  101–110
4. The software-defined networking in converged and hyperconverged infrastructures
   
   Sistemy i Sredstva Inform., 33:1 (2023),  105–113
5. On combining the software-defined networking with the network functions virtualization
   
   Sistemy i Sredstva Inform., 32:2 (2022),  36–46
6. Interrelation between the software-defined and conventional IP-networks
   
   Sistemy i Sredstva Inform., 32:1 (2022),  73–82
7. Some issues of the software-defined storage
   
   Sistemy i Sredstva Inform., 31:2 (2021),  70–79
8. Evolution of network processors
   
   Sistemy i Sredstva Inform., 31:1 (2021),  111–121
9. Some issues of software-defined data centers
   
   Sistemy i Sredstva Inform., 30:2 (2020),  103–112
10. Multicore and multithreading peculiarities in network processors
    
    Sistemy i Sredstva Inform., 30:1 (2020),  82–92
11. A practical definition of “software-defined”
    
    Sistemy i Sredstva Inform., 29:2 (2019),  85–94
12. A way to enhance throughput of packet switches built on the basis of integrated network processors
    
    Sistemy i Sredstva Inform., 29:1 (2019),  63–73
13. Virtualization overheads and factors affecting them
    
    Sistemy i Sredstva Inform., 28:3 (2018),  141–152
14. Some implicit issues of network virtualization
    
    Sistemy i Sredstva Inform., 27:3 (2017),  88–98
15. A method of packet processing in integrated network processors
    
    Sistemy i Sredstva Inform., 27:1 (2017),  108–121
16. Some issues of the SDN concept practical implementation
    
    Sistemy i Sredstva Inform., 26:1 (2016),  109–120
17. Modern trends in evolution of integrated network processor architectures
    
    Sistemy i Sredstva Inform., 24:3 (2014),  78–91
18. Some implementation aspects of the connecting medium in the decentralized packet switching architecture
    
    Inform. Primen., 3:2 (2009),  43–52
19. A design concept of domestic integrated communication microcontrollers for packet switching
    
    Inform. Primen., 3:1 (2009),  34–46
20. Time intervals as objects of a general-purpose operating system
    
    Inform. Primen., 2:4 (2008),  74–84
21. A disintegrated packet switching architecture
    
    Inform. Primen., 2:4 (2008),  2–11
22. “Многоэтажная” архитектура процессора
    
    Informatsionnye Tekhnologii i Vychslitel'nye Sistemy, 2007, no. 3,  79–87
23. Способ повышения реактивности процессора
    
    Informatsionnye Tekhnologii i Vychslitel'nye Sistemy, 2006, no. 4,  3–15
24. Способ увеличения количества портов пакетного коммутатора с помощью слотовой шины
    
    Informatsionnye Tekhnologii i Vychslitel'nye Sistemy, 2006, no. 2,  16–21
25. Prototype of multi-protocol packet switching device
    
    Sistemy i Sredstva Inform., 2006, no. 16,  449–462
26. Integrated circuits designed for packet switches and routers
    
    Sistemy i Sredstva Inform., 2006, no. 16,  436–448
27. Дезинтеграционный подход к архитектуре универсального процессора коммутации пакетов
    
    Informatsionnye Tekhnologii i Vychslitel'nye Sistemy, 2005, no. 2,  76–85