Stepchenkov Yuri Afanasievich

Publications in Math-Net.Ru

1. Self-timed counter synthesis formalization
   
   Sistemy i Sredstva Inform., 34:2 (2024),  66–82
2. Desynchronization methodology at self-timed circuit synthesis
   
   Sistemy i Sredstva Inform., 34:1 (2024),  33–43
3. Replacing synchronous triggers with self-timed counterparts during circuit desynchronization
   
   Sistemy i Sredstva Inform., 33:4 (2023),  4–15
4. Multiplexed self-timed pipeline
   
   Sistemy i Sredstva Inform., 33:2 (2023),  4–12
5. Self-timed pipeline with variable stage number
   
   Sistemy i Sredstva Inform., 33:1 (2023),  4–13
6. Approximate evaluation of the efficiency of synchronous and self-timed methodologies in problems of designing failure-tolerant computing and control systems
   
   Avtomat. i Telemekh., 2022, no. 2,  122–132
7. Synchronous and self-timed pipeline's reliability estimation
   
   Inform. Primen., 16:4 (2022),  2–7
8. Self-timed pipeline's soft error tolerance analysis
   
   Sistemy i Sredstva Inform., 32:4 (2022),  4–13
9. Self-timed shift register cases
   
   Sistemy i Sredstva Inform., 32:3 (2022),  81–91
10. The electronic component base of failure resilience digital circuits
    
    Inform. Primen., 15:4 (2021),  65–71
11. Hardware support of fast Fourier transform optimization in a recurrent signal processor
    
    Sistemy i Sredstva Inform., 31:4 (2021),  71–83
12. Recurrent signal processor hardware implementation
    
    Sistemy i Sredstva Inform., 31:3 (2021),  113–122
13. Improvement of self-time circuit soft error tilerance
    
    Inform. Primen., 14:4 (2020),  63–68
14. Multicore hybrid recurrent architecture expansion on FPGA
    
    Sistemy i Sredstva Inform., 30:4 (2020),  95–101
15. Self-timed pipeline immunity to soft errors in its combinational part
    
    Sistemy i Sredstva Inform., 30:3 (2020),  49–55
16. Self-timed combinational circuit tolerance to short-term soft errors
    
    Sistemy i Sredstva Inform., 30:2 (2020),  4–10
17. Indication optimization in multibit self-timed circuits
    
    Sistemy i Sredstva Inform., 29:4 (2019),  14–27
18. Sequential self-timed cell characterization
    
    Sistemy i Sredstva Inform., 29:3 (2019),  104–113
19. Models of fault-tolerant self-timed circuits
    
    Sistemy i Sredstva Inform., 26:4 (2016),  19–30
20. Fault-tolerant self-timed serial-parallel port: variants of realization
    
    Sistemy i Sredstva Inform., 26:3 (2016),  48–59
21. Hardware and software modeling and testing of the recurrent operational device
    
    Sistemy i Sredstva Inform., 25:4 (2015),  78–90
22. Implementation basis of exaflops class supercomputer
    
    Inform. Primen., 8:1 (2014),  45–70
23. Self-timed fused multiply-add unit: Practical implementation
    
    Sistemy i Sredstva Inform., 24:3 (2014),  63–77
24. Fused multiply-add: Methodological aspects
    
    Sistemy i Sredstva Inform., 24:3 (2014),  44–62
25. System verification tools for recurrent signal processor
    
    Sistemy i Sredstva Inform., 24:2 (2014),  55–66
26. Theoretical aspects of programming methodology development for recurrent architecture
    
    Sistemy i Sredstva Inform., 23:2 (2013),  133–153
27. Dataflow architecture model and its usage with a word recognizer program as an example
    
    Sistemy i Sredstva Inform., 22:2 (2012),  48–57
28. Exceptions fixation in recurrent dataflow processor
    
    Sistemy i Sredstva Inform., 22:1 (2012),  49–61
29. Tools for self-timed cells characterization
    
    Sistemy i Sredstva Inform., 22:1 (2012),  38–48
30. Self-timed analysis of some types of digital device
    
    Sistemy i Sredstva Inform., 21:1 (2011),  74–83
31. Hardware maintenance for digital processing of speech signals in the recurrent dataflow processor
    
    Sistemy i Sredstva Inform., 20:1 (2010),  31–47
32. System of capsule programming and debugging
    
    Sistemy i Sredstva Inform., 20:1 (2010),  24–30
33. Designing of the delay-independent computing device
    
    Sistemy i Sredstva Inform., 20:1 (2010),  5–23
34. Selection of programming languages for representing parallel algorithms for recurrent signal processor
    
    Sistemy i Sredstva Inform., 2008, no. supplementary issue,  149–158
35. Peculiarities of realization of the main modules of recurrent signal processor on the programmed logic integrated circuit (PLD)
    
    Sistemy i Sredstva Inform., 2008, no. supplementary issue,  130–148
36. The features of hybrid version of recurrent signal processor realized on the programmed logic integrated circuit (PLD)
    
    Sistemy i Sredstva Inform., 2008, no. supplementary issue,  118–129
37. Quasi self-timed realization of the device for division and square-root generation
    
    Sistemy i Sredstva Inform., 2008, no. 18,  234–260
38. Self-timed sequential circuits: Development experience and design guideline
    
    Sistemy i Sredstva Inform., 2007, no. 17,  503–529
39. System for self-timed integrated circuits testing
    
    Sistemy i Sredstva Inform., 2006, no. 16,  486–495
40. Experimental testing of some strictly self-timed circuits features
    
    Sistemy i Sredstva Inform., 2006, no. 16,  476–485
41. Universal subsystem for self-timed circuits analysis
    
    Sistemy i Sredstva Inform., 2006, no. 16,  463–475


42. The history and results of the development of home made 32-bit personal computer
    
    Sistemy i Sredstva Inform., 2008, no. 18,  281–310