RUS  ENG
Full version
PEOPLE

Morozov Nikolay V

Publications in Math-Net.Ru

  1. Self-timed up counter implementation

    Sistemy i Sredstva Inform., 34:3 (2024),  123–135
  2. Self-timed counter synthesis formalization

    Sistemy i Sredstva Inform., 34:2 (2024),  66–82
  3. Desynchronization methodology at self-timed circuit synthesis

    Sistemy i Sredstva Inform., 34:1 (2024),  33–43
  4. Replacing synchronous triggers with self-timed counterparts during circuit desynchronization

    Sistemy i Sredstva Inform., 33:4 (2023),  4–15
  5. Self-timed pipeline with variable stage number

    Sistemy i Sredstva Inform., 33:1 (2023),  4–13
  6. Self-timed pipeline's soft error tolerance analysis

    Sistemy i Sredstva Inform., 32:4 (2022),  4–13
  7. Self-timed shift register cases

    Sistemy i Sredstva Inform., 32:3 (2022),  81–91
  8. Recurrent signal processor hardware implementation

    Sistemy i Sredstva Inform., 31:3 (2021),  113–122
  9. Multicore hybrid recurrent architecture expansion on FPGA

    Sistemy i Sredstva Inform., 30:4 (2020),  95–101
  10. Self-timed pipeline immunity to soft errors in its combinational part

    Sistemy i Sredstva Inform., 30:3 (2020),  49–55
  11. Self-timed combinational circuit tolerance to short-term soft errors

    Sistemy i Sredstva Inform., 30:2 (2020),  4–10
  12. Indication optimization in multibit self-timed circuits

    Sistemy i Sredstva Inform., 29:4 (2019),  14–27
  13. Sequential self-timed cell characterization

    Sistemy i Sredstva Inform., 29:3 (2019),  104–113
  14. Hardware and software modeling and testing of the recurrent operational device

    Sistemy i Sredstva Inform., 25:4 (2015),  78–90
  15. Self-timed fused multiply-add unit: Practical implementation

    Sistemy i Sredstva Inform., 24:3 (2014),  63–77
  16. System verification tools for recurrent signal processor

    Sistemy i Sredstva Inform., 24:2 (2014),  55–66
  17. Tools for self-timed cells characterization

    Sistemy i Sredstva Inform., 22:1 (2012),  38–48
  18. Particularities of taxonomic self-timed circuits analysis

    Sistemy i Sredstva Inform., 21:1 (2011),  92–104
  19. Self-timed analysis of some types of digital device

    Sistemy i Sredstva Inform., 21:1 (2011),  74–83
  20. Designing of the delay-independent computing device

    Sistemy i Sredstva Inform., 20:1 (2010),  5–23
  21. Quasi self-timed realization of the device for division and square-root generation

    Sistemy i Sredstva Inform., 2008, no. 18,  234–260
  22. System for self-timed integrated circuits testing

    Sistemy i Sredstva Inform., 2006, no. 16,  486–495
  23. Universal subsystem for self-timed circuits analysis

    Sistemy i Sredstva Inform., 2006, no. 16,  463–475


© Steklov Math. Inst. of RAS, 2024